The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. However, these advances have increased the complexity of processing and manufacturing ICs and, for these advances to be realized, similar developments in IC processing and manufacturing are needed.
In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. Such scaling-down has also required that the various processes utilized to fabricate the IC features with minimal dimensional and geometrical variations. For advanced processing technologies, substrate planarity enables patterning of fine features. Conventional processing techniques could leave regions with varying step heights and undesirable film(s) on the substrate. These varying step heights and un-desirable residual film(s) contribute to poor patterning and reduced yield. It is within this context, the following disclosure arises.